LDMOS (laterally diffused metal oxide semiconductor) transistors are commonly used in RF/microwave power amplifiers, e.g., in base-stations where the requirement is for high output power with a corresponding drain to source breakdown voltage usually above 60 volts. These transistors are fabricated by growing an epitaxial silicon layer on a more highly doped silicon substrate.
A typical LDMOS is shown in FIG. 1, which shows a n-epitaxial layer 100 grown on a p-epitaxial layer 102, which, in turn is grown on a p-substrate 104. In this depiction, an n-buried layer 106 is formed in the n-epi 100 on top of the p-epi 102. The LDMOS includes an n+ drain 110 formed in an n-well 112 with an n-drift region 114 extending underneath the poly gate 120. As shown in FIG. 1, the n+ source region 122 is formed in a p-body 124. A p+ implant 126 provides a contact to the p-body. The gate 120 is formed on a gate oxide 130.
One of the drawbacks of an LDMOS device is the conduction loss in the inherent body diode of the device. Also, due to minority carrier accumulation the reverse recovery time is slow. Hence the LDMOS suffers from high dynamic losses due to the slow reverse recovery times.
One prior art solution is to include an external Schottky diode. However due to the high inductance of the package and printed circuit board the benefits are diminished. This is illustrated in the circuit diagram of FIG. 2, which shows a buck converter circuit comprising a high side LDMOS device 200 and a low side LDMOS 202, with external Schottky diode 210. The inductance of the package and the inductance of the PCB are depicted as parasitic stray inductances Lp 220. As shown in FIG. 2, the LDMOS devices 200, 202 both define an internal body diode 240, 242, respectively. The inductance of the external Schottky diode can be reduced by placing the Schottky diode in the same package as the MOSFET, however this requires two devices in the same package, which requires a large amount of space.